(1) Field of the Invention
This invention relates to a circuit for correcting the duty cycle of a clock signal and more specifically to a circuit which converts a clock signal having a duty cycle of other than 50% to a 50% duty cycle.
(2) Description of the Related Art
Two aspects of a clock signal that are of key importance in many circuit applications are the clock frequency and the clock duty cycle. The clock duty cycle can become distorted through circuit interaction and circuits which can restore the duty cycle to a desired level are of significant importance.
U.S. Pat. No. 5,614,855 to Lee, et al. describes a delay locked loop, DLL, in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, such as 50%.
U.S. Pat. No. 5,757,218 to Blum describes a duty cycle correction circuit that facilitates correction of clock signal duty cycles, including correcting for errors introduced by intervening devices in the clock signal distribution network. The duty cycle correction circuit has a clock chopper circuit, a duty cycle comparator circuit, and a control circuit. The duty cycle comparator circuit compares the duty cycle of the clock signal with the duty cycle of a reference signal. The control circuit adjusts the clock chopper circuit based upon the duty cycle comparison, resulting in an output with a corrected duty cycle.
U.S. Pat. No. 5,945,862 to Donnelly, et al. describes circuitry for the delay adjustment of a clock signal. The circuitry performs duty cycle correction of the input clock and the selected output clock.
A paper entitled xe2x80x9cA Portable Digital DLL For High-Speed CMOS Interface Circuitsxe2x80x9d by B. W. Garlepp, et al., IEEE Journal of Solid-State Circuits, pp. 632-644, May 1999, Vol. 34, No. 5, describes a digital delay-locked loop, DLL, that achieves infinite phase range and 40 picosecond worst case phase resolution at 400 MHz which was developed in a 3.3 volt, 0.4 micron standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers.
A paper entitled xe2x80x9cA 2.5 V CMOS Delay-Locked Loop for 18 Mbit, 500 Megabyte/s DRAMxe2x80x9d, by T. H. Lee, et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, December 1994, pages 1491-1496 describes clock recovery circuits specifically designed for a hostile noise environment. These circuits implement a delay-locked loop thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed in signal and control paths to decrease noise sensitivity. Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction.
A paper entitled xe2x80x9cA 2.5 V Delay-Locked Loop for an 18 Mb 500 MB/s DRAMxe2x80x9d, by T. H. Lee, et al., IEEE International Solid-State Circuits Conference, July 1994, pp. 300-301 describes a pair of delay-locked loops, DLL, one for transmitting data and one for receiving data. The pair of DLL circuits provide accurate timing in the noisy environment of DRAMs to allow data transfer rates exceeding 500 Mb/s/pin at 2.5 volts.
In many circuit applications, such as switch capacitor circuits, two aspects of the clock signal can have a significant effect on the design and performance of the circuit. These two aspects of the clock signal are the clock frequency and the duty cycle. The clock frequency is usually set by the overall circuit application and not subject to change. The duty cycle of the clock is initially determined by the clock generator. The duty cycle is defined as the ratio of the time the clock pulse is at the high level to the clock period. A clock signal that is at the high level for one half of the clock period and the low level for one half the clock period has a 50% duty cycle. A 50% duty cycle is usually desirable because it makes the most efficient use of the times the clock signal is at the high level and at the low level.
As the clock signal propagates through circuits the clock signal duty cycle can become distorted. A simple circuit to restore the clock signal duty cycle to the desired value, such as 50% is very desirable.
It is a principle objective of this invention to provide a circuit which produces an output clock signal having a 50% duty cycle for an input clock signal having a wide range of duty cycles.
This objective is achieved by a circuit having an input node, an output node, a first node, a second node, and a reference node. A first capacitor is connected between the first node and the reference node. A second capacitor is connected between the second node and the reference node. The input clock signal is fed to the input node and the output clock signal is taken from the output node. When the input clock signal is at the low level the first capacitor is charged at a rate which is inversely proportional to the voltage drop across the second capacitor. When the input clock signal is at the high level the first capacitor is discharged at a rate which is directly proportional to the voltage drop across the second capacitor.
When the voltage drop across the first capacitor exceeds a threshold voltage the voltage at the output node is at the low level. When the voltage drop across the first capacitor is less than the threshold voltage the voltage at the output node is at the high level. When the voltage at the output node is at the low level the second capacitor is charged at a constant rate by a current source. When the voltage at the output node is at the high level the second capacitor is discharged at a constant rate by another current source. The output clock signal is taken from the output node.
The voltage drop across the first capacitor exhibits a sawtooth waveform, increasing when the input clock signal is at the low level and decreasing when the input clock signal is at the high level. The charging rate and the capacitance of the second capacitor are chosen so that the voltage drop across the second capacitor exhibits only slight variations. This circuit produces an output clock signal having a very nearly 50% duty cycle for a wide range of duty cycles for the input clock signal. The circuit and the details of the generation of the output clock signal will be described in greater detail with reference to the drawings.